The present invention relates to semiconductor devices and their fabrication and more particularly to semiconductor devices in which a stress is applied to the semiconductor device.
In fabricating integrated circuits in conventional bulk semiconductor wafers, wells of either p-type or n-type conductivity are implanted in a substrate of the opposite conductivity. However, in complementary metal oxide semiconductor (CMOS) technology, both p-type and n-type wells are utilized. Source/drain regions are formed by implanting diffusion regions of the opposite n-type or p-type conductivity as the wells to form metal-oxide-semiconductor field effect transistors (MOSFETs). The carrier mobility in a transistor can be increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein. An increase in the performance of an n-type field effect transistor (NFET) can be achieved by applying a tensile longitudinal stress to the conduction channel of the NFET. An increase in the performance of a p-type field effect transistor (PFET) can be achieved by applying a compressive longitudinal stress to the conduction channel of the PFET.
A stress-imparting film, also referred to herein as a “stressed” film, can be deposited to cover a semiconductor device region to impart a stress thereto for enhancing the conductivity of a transistor, for example, an NFET or a PFET device. Silicon nitride is one material, among others, which can be deposited in such way that the resulting material layer imparts either a tensile stress or a compressive stress to a layer of a second material with which it is in contact. To improve the conductivity of both an NFET and a PFET, a tensile stress-imparting nitride can be formed to cover an NFET device region and a compressive stress-imparting nitride can be formed to cover a PFET device region.
From a fabrication point of view, such a goal can be accomplished by applying two films, each having a different internal stress. In such case, one stressed film 102 can be patterned with an overlying oxide layer 103, after which a second film 104 is deposited and then patterned to produce the overlapped films 100 at the boundary 220, as illustrated in the cross-sectional depiction of FIG. 1. The overlapped films 100, however, can create certain problems.
One such problem concerns the fabrication of a contact via 210 through dielectric layer 212 for conductively contacting the silicided polysilicon conductor 225 overlying a shallow trench isolation (STI) region 110 at the boundary 220 between two differently stressed films 102, 104. The etching of the contact hole at that boundary 220 can be difficult to perform while etching other contact holes, such as the contact hole for contact via 230 to the silicide region 203 that overlies the active device region 202 (FIG. 2). The difficulty arises because of the difference between the relatively large thickness of the aggregated films 102, 103 and 104 that overlie the silicided polyconductor 225, as compared to the smaller thickness of the stressed film 102 which overlies the silicide layer 203 above the active device region 202.
Because of this difference in the total film thicknesses, the contact hole for the contact via 210 is less likely to be etched to a sufficient depth to properly contact the silicided polysilicon conductor 225. A contact open failure can result, as best seen at 220 in FIG. 1. A contact open failure is one in which much higher than normal contact resistance occurs at the interface between the contact via 210 and the polysilicon conductor. A contact open failure can occur when the contact hole fails to be etched sufficiently to contact the silicide layer 222. On the other hand, extending the etching depth to prevent a contact open failure with respect to the contact via 210 could also cause the silicide region 203 and/or the active device region 202 to be excessively over-etched. It is desirable that the contact hole for forming the contact via 230 be etched to a depth that falls just below the major surface 205 of the silicide region 203. When the contact hole is over-etched excessively, i.e., to a depth below the silicide layer 203, the semiconductor device region 202 can exhibit excessive junction leakage.
Consequently, a need exists for a structure and an associated method of fabricating a semiconductor device in which more than one stressed film can be provided, while permitting contact holes to both the silicided polyconductor and to the active device region to be etched with less difficulty.